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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Product Features
* * * * * * * * * * * * Intel's 810E clock solution 3 copies of CPU Clock (CPU[0:1] and CPU_ITP) 9 copies of SDRAM Clock (SDRAM[0:7] and DCLK) 8 copies of PCI Clock 2 copies of 3V66 Clock 2 copies of APIC Clock, synchronous to PCI Clock 1 REF Clock 1 USB Clock (Non SSC) 1 DOT Clock (Non SSC) Power Down Feature Spread Spectrum Support SMBUS Support for turning off unused clocks
Frequency Table (MHz)
SEL2 X X 0 0 1 SEL1 0 0 1 1 1 SEL0 0 1 0 1 X CPU Tristate 66.6 100 133.3
Table 1
SDRAM Tristate 100 100 100
PCI Tristate 33.3 33.3 33.3
Test mode (see table2)
Note: The following clocks remain fixed frequencies except in Test Mode. 3V66=66.6MHz, USB/DOT=48MHz, REF=14.318MHz and IOAPIC=33.3MHz.
Block Diagram
XIN 36pF 300K 36pF XOUT 1 VDD REF / SE L2
Pin Configuration
SEL2/REF VDD XIN XOUT VSS VSS 3V660 3V661 VDD VDD PCI0_ICH PCI1 PCI2 VSS PCI3 PCI4 VSS PCI5 PCI6 PCI7 VDD VDDA VSSA VSS USB DOT VDD SEL0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VSS IOAPIC0 IOAPIC1 VDDI CPU0 VDDC CPU1 CPU2_ITP VSS VSS SDRAM0 SDRAM1 VDDS SDRAM2 SDRAM3 VSS SDRAM4 SDRAM5 VDDS SDRAM6 SDRAM7 VSS DCLK VDD PD# SCLK SDATA SEL1
VDDI s2 Rin VDDC SCLK SDATA i2c-clk i2c-data cpu 3 CPU(0:2) ioapic 2 IOAP IC(0:1)
VDDS VDD SEL1 SEL0 PD#
VDD
sdram s1
9 VDD
SDRA M(0:7), DC LK
C 9 8 1 2
s0 pwr_dwn#
66m
2 VDD
3V66(0:1)
pci PLL1 Rin PD# 48
8 VDD 1 VDD 1
PCI(0:7)
DOT
USB
i2c-clk i2c-data PLL2
Fig.1
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Pin Description
PIN No. 1 Pin Name SEL2/REF PWR VDD I/O I/O TYPE Description 3.3V 14.318 MHz clock output. This pin also serves as the select strap (associates with SEL0 & 1, see app. note page 5) for clock frequencies during power up. Refer to Table 1 for detail. This pin has an internal pull-down (Typ. 70K). 14.318MHz Crystal input 14.318MHz Crystal output 3.3V PCI clock outputs
3 4 11, 12, 13, 15, 16, 18, 19, 20 7, 8 25 26 28, 29 30 31 32 34 36, 37, 39, 40, 42, 43, 45, 46 49, 50, 52 54, 55 2, 9, 10, 21, 27, 33 22 23 51, 53 5, 6,14, 17, 24, 35, 41, 47, 48, 56 38, 44
XIN XOUT PCI0/ICH PCI(1..7) 3V66(0,1) USB DOT SEL(0,1) SDATA SCLK PD# DCLK SDRAM(7..0)
VDD VDD VDD
I O O
OSC1
VDD VDD VDD VDD VDD VDD VDD VDD VDDS
O O O I I I I O O
3.3V Fixed 66.6 MHz clock outputs 3.3V Fixed 48 MHz clock outputs 3.3V Fixed 48 MHz clock outputs 3.3V LVTTL compatible inputs for logic selection. Has an internal pull-up (Typ. 250K) IC compatible SDATA input. Has an internal pull-up (>100K) IC compatible SCLK input. Has an internal pull-up (>100K) 3.3V LVTTL compatible input. Device enters powerdown mode When held LOW. Has an internal pull-up (>100K) 3.3V output running 100MHz 3.3V output running 100MHz. All SDRAM outputs can be turned off through SMBUS. 2.5V Host bus clock outputs. 66, 100 or 133MHz depending on state of SEL(2..0) 2.5V clock outputs running rising edge synchronous with the PCI clock. 3.3V Power Supply Analog circuitry 3.3V Power Supply Analog circuitry power supply Ground pins. 2.5V Power Supply's Common Ground pins.
CPU(2)_ITP, CPU(1,0) IOAPIC(1,0) VDD VDDA VSSA VDDC, VDDI VSS
VDDC VDDI -
O O
-
VDDS
-
-
3.3V power support for SDRAM clock output drivers.
A bypass capacitor (0.1F) should be placed as close as possible to each positive power pin. If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07053 Rev. **
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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Test Mode Function
Test Mode Functionality SEL2 SEL1 SEL0 x 0 1
CPU TCLK/2
SDRAM TCLK/2
3V66 TCLK/3
Table 2
PCI TCLK/6
48 MHz TCLK/2
REF TCLK
IOAPIC TCLK/6
Note: TCLK is a test clock over driven on the XIN input during test mode.
Power Management Functions
Power Management on this device is controlled by a single pin, PD# (pin32). When PD# is high (default) the device is in running and all signals are active. When PD# is asserted (forced) low, the device is in shutdown (or in power down) mode and all power supplies (3.3V and 2.5V except for VDDA/pin 27) may be removed. When in power down, all outputs are synchronously stopped in a low state (see Fig.2 below), all PLL's are shut off, and the crystal oscillator is disabled. When the device is shutdown the IC function is also disabled.
Power Management Timing
0nS 10nS 20nS 30nS 40nS 50nS
CPU 100MHz 3V66 PCI IOAPIC PWRDN#
SDRAM 100MHz CLOCK REF 14.3MHz
Undefined Undefined Undefined
66MHz 33MHz 33MHz
USB
48MHz Fig.2
Power Management Current
PD#, SEL[2..0] (CPU Clock) 0XXX (Power down) 1010 (66MHz) 1011 (100MHz) 111X (133MHz) Maximum 2.5 Volt Current Consumption (VDD2.5 =2.625) 100 A 70 mA 100 mA 133 mA
Table 3
Maximum 3.3 Volt Current Consumption (VDD3.3 = 3.465 V) 200 A 280 mA 280 mA 280 mA
When exiting the power down mode, the designer must supply power to the VDD pins first, a minimum of 200mS before releasing the PD# pin high.
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07053 Rev. **
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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Clock Synchronization and Phase Alignment
This device incorporates IOAPIC clock synchronization. With this feature, the IOAPIC clocks are derived from the CPU clock. The IOAPIC clock lags the CPU clock by the specified 1.5 to 3.5 nSec. Figure 3 shows the relationship between the CPU and IOAPIC clocks.
Device Clock Phase Relationships
0nS
10nS
20nS
30nS
40nS
CPU CLOCK
66MHz
2.5nS
CPU CLOCK 100MHz CPU CLOCK 133MHz
7.5nS 5nS
Sync 5nS
SDRAM CLOCK 100MHz
3V66 CLOCK 66MHz PCI CLOCK 33MHz1.5~3.5nS IOAPIC CLOCK 33MHz
Fig.3
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Power on Bi-Directional Pins
Power Up Condition: Pin1 is a Power up bi-directional pin and is used for selecting the host frequency in page 1, table 1. During power-up of the device, this pin is in input mode (see Fig 4, below), therefore; it is considered an input select pins internal to the IC. After a settling time, the selection data is latch into the internal control register and this pin becomes a clock output.
POWER SUPPLY RAMP VDD RAIL
REF / SEL2 (Pin 1)
Hi-Z INPUTS
-
TOGGLE OUTPUTS
SELECT DATA IS LATCHED INTO REGISTER THEN PIN BECOMES A REF CLOCK OUTPUT SIGNAL Fig.4
Strapping Resistor Options: The power up bi-directional pins have a large value pull-down each (70K), therefore, a selection "0" is the default. If the system uses a slow power supply (over 5mS settling time), then it is recommended to use an external Pull-down in order to insure a low selection. Fig. 5 If a selection "0" is desired, then a jumper is placed on JP1 to a 10K resistor as implemented as shown in Fig.5. Please note the selection resistor (Rdn) is placed before the Damping resistor (Rd) close to the pin.
Vdd
JP1 Jumper 3 2
1 Rsel 10K
IMI C9812 Bidirectional
Rd Load
Fig. 5
70K
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07053 Rev. **
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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
2-Wire SMBUS Control Interface
The 2-wire control interface implements a write slave only interface according to SMBus specification. (See Fig. 7 / P. 8). The device can be read back by using standard SMBUS command bytes. Sub addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported. During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer cycle is an 8-bit address. W#=0 in write mode. The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on the SDATA wire following reception of each byte. Data is transferred MSB first at a max rate of 100kbits/S. The device will not respond to any other control interface conditions, and previously set control registers are retained.
SMBUS Test Circuitry
+ 5V 2.2 K
Device under Test SDATA
DATAIN
+ 5V 2.2 K + 5V 2.2 K
SCLK
DATAOUT
CLOCK
Fig.6 Note: Buffer is 7407 with VCC @ 5.0 V
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Serial Control Registers
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true power up. Bytes are set to the values shown only on true power up. Following the acknowledge of the Address Byte, two additional bytes must be sent: 1) "Command Code " byte, and 2) "Byte Count" byte. Although the data (bits) in these two bytes are considered "don't care"; they must be sent and will be acknowledged. After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1, and Byte2) will be valid and acknowledged.
Byte 0: CPU Clock Register (1=Enable, 0=Disable, Default=07) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 1 1 1 Pin# 26 25 49 Description Reserved Reserved Reserved Reserved Spread spectrum mode DOT USB CPU2_ITP Byte 1: SDRAM Clock Register (1=Enable, 0=Disable, Default=FF) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 36 37 39 40 42 43 45 46 Description SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
Byte 2: PCI Clock Register (1=Enable, 0=Disable, Default=FE) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 0 Pin# 20 19 18 16 15 13 12 Description PCI7 PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 Reserved
Byte 3: Reserved Register (Default=00) Byte 4: Reserved Register (Default=00) Byte 5: SSCG Control Register (Default=00) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Pin# Description Spread Mode (0=down, 1=center) Ref. Table 4 Ref. Table 4 Reserved Reserved Reserved Reserved Reserved
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
SDATA IS OUTPUT PIN SDATA IS INPUT PIN ACK ACK COMMAND BYTE (DON'TCARE)
1
1
0
1
0
0
1
0
SDATA MSB LSB
SCLK
START CONDITION
8
CONTINUED ACK COUNT BYTE (DON'TCARE) BYTE 0 (VALID DATA) ACK BYTE N (LAST VALID DATA) ACK
CONTINUED
8
8
8
STOP CONDITION
Figure 7 SMBUS Communications Waveforms
Test and Measurement Condition
Output under Test Probe
Load Cap
3.3V signals
tDC
-
2.5V signals
tDC
-
3.3V 2.5V 2.4V 2.0V 1.25V
1.5V
0.4V 0V
0.4V 0V
Tr
Tf
Tr
Tf
Fig.8 Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore spreading the same amount of energy over a spectrum. This technique is achieved by modulating the clock down from (Fig.9A) or around the center (Fig.9B) of its resting frequency by a certain percentage (which also determines the energy distribution bandwidth). In this device, Spread Spectrum is enabled by setting SMBUS byte0, bit3 = 1. The default of the device at power up keeps the Spread Spectrum disabled, it is therefore, important to have SMBUS accessibility to turn-on the Spread Spectrum function. Once the Spread Spectrum is enabled, the spread bandwidth option is selected by SST(0:2) in SMBUS byte 5, bits 5, 6 & 7 following tables 4A, and 4B below. In Down Spread mode the center frequency is shifted down from its rested (non-spread) value by 1/2 of the total spread %. (eg.: assuming the center frequency is 100MHz in non-spread mode; when down spread of -0.5% is enabled, the center frequency shifts to 99.75MHz.). In Center Spread mode, the Center frequency remains the same as in the non-spread mode.
Down Spread Center Spread
Fig.9A
Fig.9B
Spread Spectrum Selection Tables
IC BYTE5 Bit[7:5] 100 101 110 111 Table 4A Center Frequency (MHz) 66/100/133.3 66/100/133.3 66/100/133.3 66/100/133.3 Spread % 0.25 0.35 0.5 0.7 IC BYTE5 Bit[7:5] 000 001 010 011 Table 4B Down Frequency (MHz) 66/100/133.3 66/100/133.3 66/100/133.3 66/100/133.3 Spread % - 0.5 - 0.7 - 1.0 - 1.5
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07053 Rev. **
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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Maximum Ratings
This device contains circuitry to protect the inputs Maximum Input Voltage Relative to VSS: VSS - 0.3V Maximum Input Voltage Relative to VDD: VDD + 0.3V Storage Temperature: Operating Temperature: Maximum ESD protection Maximum Power Supply: -65C to + 150C 0C to +70C 2KV 5.5V against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)DC Parameters
Characteristic
Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Current (@VIL = VSS) Input High Current (@VIL =VDD) Tri-State leakage Current Dynamic Supply Current Dynamic Supply Current Static Supply Current Input pin capacitance Output pin capacitance Pin capacitance Clock Stablization Time Crystal pin capacitance Crystal DC Bias Voltage Crystal Startup time
Symbol
VIL1 VIH1 VIL2 VIH2 IIL IIH Ioz Idd3.3V Idd2.5V Isdd Cin Cout Lpin tstab Cxtal VBIAS Txs
Min
2.0 2.2 -66 3 32 0.3Vdd -
Typ
-
Max
1.0 1.0 -5 5
Units
Vdc Vdc Vdc Vdc A A A mA mA A pF pF nH mSec pF V
S
Conditions
Note 1 Note 2 For internal Pull up resistors, Notes 1,3 Sel2 = Sel1 = Sel0 = 1, Note 4 Sel2 = Sel1 = Sel0 = 1, Note 4 Sel2 = Sel1 = Sel0 = x, Note 4
34 Vdd/2 -
10 280 100 300 5 6 7 38 0.7Vdd 40
Measured from VDD - 3.15 volts Measured from Pin to Ground. Note 5 From Stable 3.3V power supply.
VDD=VDDS = 3.3V 5%, VDDC = VDDI = 2.5 5%, TA = 0 to +70C
Note1: Note2: Note3: Note4: Note5: Applicable to input signals: Sel(0:1), PD# Applicable to Sdata, and Sclk. Although internal pull-up resistors have a typical value of 250K, this value may vary between 200K and 500K. Internal Pull-down resisters are typically 70K in value. All outputs loaded as per table below. Although the device will reliably interface with crystals of a 17pF - 20pF CL range, it is optimized to interface with a typical CL = 18pF crystal specifications.
Clock Name CPU, IOAPIC, REF, USB PCI, SDRAM, 3V66(0,1) DOT Table 5.
Max Load (in pF) 20 30 15
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
AC Parameters
133 MHz Host Symbol TPeriod THIGH TLOW Tr / Tf TSKEW TCCJ TPeriod THIGH TLOW Tr / Tf TCCJ TPeriod THIGH TLOW Tr / Tf TSKEW TCCJ TPeriod THIGH TLOW Tr / Tf TSKEW TCCJ TPeriod Tr / Tf TCCJ TPeriod Tr / Tf TCCJ tpZL, tpZH tpLZ, tpZH tstable Parameter CPU(0:1) period CPU(0:1) high time CPU(0:1) low time CPU(0:1) rise and fall times CPU0 to CPU1 Skew time CPU(0:1) Cycle to Cycle Jitter APIC(0:1) period APIC(0:1) high time APIC(0:1) low time APIC(0:1) rise and fall times APIC(0:1) Cycle to Cycle Jitter 3V66-(0:1) period 3V66-(0:1) high time 3V66-(0:1) low time 3V66-(0:1) rise and fall times 3V66-0 to 3V66-1 Skew time 3V66-(0:1) Cycle to Cycle Jitter PCI(0:7) period PCI(0:7) period PCI(0:7) low time PCI(0:7) rise and fall times (Any PCI clock) to (Any PCI clock) Skew time PCI(0:7) Cycle to Cycle Jitter 48MHz period ( conforms to +167ppm max) 48MHz rise and fall times 48MHz Cycle to Cycle Jitter REF period REF rise and fall times REF Cycle to Cycle Jitter Output enable delay (all outputs) Output disable delay (all outputs) All clock Stabilization from power-up Min 7.5 1.87 1.67 0.4 60.0 25.5 25.3 0.4 15.0 5.25 5.05 0.4 30.0 12.0 12.0 0.5 20.8299 1.0 69.8413 1.0 1.0 1.0 Max 8.0 1.6 175 250 1.6 500 16.0 1.6 250 500 2.0 500 500 20.8333 4.0 500 71.0 4.0 1000 10.0 10.0 3 100 MHz Host Min 10.0 3.0 2.8 0.4 60.0 25.5 25.3 0.4 15.0 5.25 5.05 0.4 30.0 12.0 12.0 0.5 20.8299 1.0 69.8413 1.0 1.0 1.0 Max 10.5 1.6 175 250 N/S 1.6 500 16.0 1.6 250 500 2.0 500 500 20.8333 4.0 500 71.0 4.0 1000 10.0 10.0 3 Units nS nS nS nS pS pS nS nS nS nS pS nS nS nS nS pS pS nS nS nS nS pS pS nS nS pS nS nS pS nS nS mS Notes 5, 6, 8 6,10 6, 11 6, 7 6, 8, 9 6, 8, 9 5, 6, 8 6,10 6, 11 6, 7 6, 8, 9 5, 6, 8 6,10 6, 11 6, 7 6, 8, 9 6, 8, 9 5, 6, 8 6,10 6, 11 6, 7 6, 8, 9 6, 8, 9 5, 6, 8 6, 7 6, 8, 9 5, 6, 8 6, 7 6, 8 13 13 12
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Switching Characteristics
Characteristic Output Duty Cycle CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI PCI to IOAPIC Skew (CPU0-CPU1) Skew (SDRAM-SDRAM) Skew (APIC-APIC) Skew (3V66-3V66) Skew (PCI - PCI) Cycle to Cycle Jitter Cycle to Cycle Jitter Cycle to Cycle Jitter
Note 6: Note 7:
Symbol TPD1 TPD2 TPD3 tPD tPD tSKEW1 tSKEW2 tSKEW3 tSKEW4 TSKEW5 P1 P2 P3
Min 45 1.5 -
Typ 50 0 -
Max 55 500 500 500 1 175 250 250 175 500 250 500 1,000
Units % pS pS pS nS nS pS pS pS pS pS pS pS pS
Conditions Note 6 CPU = 133.3MHz, Notes 6, 7 CPU = 133.3MHz, Notes 6, 7 CPU = 66.6/100/133.3MHz Notes 6, 7 CPU = 66.6/100/133.3MHz Notes 6, 7 CPU = 66.6/100/133.3MHz Notes 6, 7 see Notes 6, 7 see Notes 6, 7
CPU, and SDRAM, Notes 6 & 7 IOAPIC, USB, DOT, 3V66, PCI, Notes 6, 7 REF, Notes 6& 7
VDD=VDDS=3.3V 5%, VDDC=VDDI=2.55%, TA=0 to 70C
All outputs loaded as per table 5 below. Probes are placed on the pins and taken at 1.5V levels for 3.3V signals and at 1.25V for 2.5V signals. This measurement is applicable with Spread Spectrum ON or OFF.
Output Buffer Characteristics Buffer Characteristics for CPU
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Dynamic Output Impedance Rise Time Min Between 0.4 and 2.0 V Fall Time Max Between 0.4 and 2.0 V Symbol IOH1 IOH2 IOL1 IOL1 Z0 Tr Tf Min -28 -26 12 27 13.5 0.4 0.4 Typ -61 -58 24 56 Max -107 -101 40 93 45 1.6 1.6 Units mA mA mA mA nS nS Conditions Vout =VDDC - 0.4V Vout = 1.2 V Vout = 0.4 V Vout = 1.2 V 20pF Load 20pF Load
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Output Buffer Characteristics (Cont.) Buffer Characteristics for PCI, 3V66 and DOT
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Dynamic Output Impedance Rise Time Min Between 0.4 and 2.4 V Fall Time Max Between 0.4 and 2.4 V Symbol IOH1 IOH2 IOL1 IOL1 Z0 Tr Tf Min -33 -30 9.4 28 12 0.5 0.5 Typ -58 -54 18 55 Max -194 -184 38 148 55 2.0 2.0 Units mA mA mA mA nS nS Conditions Vout =VDDC - 1.0 V Vout = 1. 5 V Vout = 0.4 V Vout = 1.5 V 30pF Load 30pF Load
Buffer Characteristics for USB and REF
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Dynamic Output Impedance Rise Time Min Between 0.4 and 2.4 V Fall Time Max Between 0.4 and 2.4 V Symbol IOH1 IOH2 IOL1 IOL1 Z0 Tr Tf Min -29 -27 9 26 20 1.0 1.0 Typ -46 -43 13 39 Max -99 -92 27 79 60 4.0 4.0 Units mA mA mA mA nS nS Conditions Vout =VDD - 1.0 V Vout = 1. 5 V Vout = 0.4 V Vout = 1.5 V 20pF Load 20pF Load
Buffer Characteristics for IOAPIC
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Dynamic Output Impedance Rise Time Min Between 0.4 and 2.0 V Fall Time Max Between 0.4 and 2.0 V Symbol IOH1 IOH2 IOL1 IOL1 Z0 Tr Tf Min -28 -26 12 28 13.5 0.4 0.4 Typ -61 -58 24 60 Max -107 -107 40 100 45 1.6 1.6 Units mA mA mA mA nS nS 20pF Load 20pF Load Conditions Vout =VDDI - 0.5V Vout = 1. 0 V Vout = 0.4 V Vout = 1.4 V
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Output Buffer Characteristics (Cont.) Buffer Characteristics for SDRAM
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Dynamic Output Impedance Rise Time Min Between 0.4 and 2.4 V Fall Time Max Between 0.4 and 2.4 V Symbol IOH1 IOH2 IOL1 IOL1 Z0 Tr Tf Min -72 -68 23 64 10 0.4 0.4 Typ -116 -110 34 98 Max -198 -188 53 159 24 1.6 1.6 Units mA mA mA mA nS nS 30pF Load 30pF Load Conditions Vout =VDD - 1. 0 V Vout = 1. 4 V Vout = 0.4 V Vout = 1.5 V
VDD=VDDS=3.3V 5%, VDDC=VDDI=2.55%, TA=0 to 70C
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Suggested Crystal Oscillator Parameters
Characteristic Frequency Tolerance Symbol Fo TC TS TA Mode Load Capacitance Effective Series resistance (ESR) Power Dissipation OM CL R1 DL Min 12.00 Typ 14.31818 18 40 Max 16.00 +/-100 +/- 100 5 0.10 pF Ohms mW Units MHz PPM PPM PPM Note 1 Stability (Ta -10 to +60C) Note 1 Aging (first year @ 25C) Note 1 Parallel Resonant, Note 1 The crystal's rated load. Note 1 Note 1 Conditions
Note 1 Crystal's internal package Shunt Capacitance CO -8 pF capacitance (total) Note1: For best performance and accurate Center frequencies of this device, It is recommended but not mandatory that the chosen crystal meets these specifications For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit traces, the clock generator and any onboard discrete load capacitors. Budgeting Calculations Device pin capacitance: Cxtal = 34pF In order to meet the specification for CL = 18pF following the formula:
CL =
C XIN xC XOUT C XIN + C XOUT
Then the board trace capacitance between Xin and the crystal should be no more than 2pF. (same is applicable to the trace between Xout and the crystal) In this case the total capacitance from the crystal to Xin will be 36pF. Similarly the total capacitance between the crystal and Xout will be 36pF. Hence using the above formula:
CL =
36 pFx36 pF = 18 pF 36 pF + 36 pF
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01 Page 15 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Package Drawing and Dimensions 56 Pin SSOP Outline Dimensions
INCHES SYMBOL C L E H A A1 A2 B C D D A2 A1 B
e
a
MILLIMETERS MAX 0.110 0.016 0.092 0.0135 0.010 .730 0.299 MIN 2.41 0.20 2.24 0.203 0.127 18.29 7.42 NOM 2.59 0.31 2.29 0.254 18.42 7.52 0.635 BSC 0.410 0.040 8 0.100 10.16 0.61 0 2.16 10.31 0.81 5 2.36 10.41 1.02 8 2.54 MAX 2.79 0.41 2.34 0.343 0.254 18.54 7.59
MIN 0.095 0.008 0.088 0.008 0.005 .720 0.292
NOM 0.102 0.012 0.090 0.010 .725 0.296 0.025 BSC
E e H L a X
A
0.400 0.024 0 0.085
0.406 0.032 5 0.093
Ordering Information
Part Number C9812DYB Marking: Example: Package Type 56 PIN SSOP Cypress C9812 Date Code, Lot # Production Flow Commercial, 0 to 70C
C9812DYB Flow B = Commercial, 0 to 70C Package Y = SSOP Revision Device Number
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01 Page 16 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Notice
Cypress Semiconductor Corporation reserves the right to change or modify the information contained in this data sheet, without notice Cypress Semiconductor Corporation does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress Semiconductor Corporation does not convey any license under its patent rights nor the rights of others Cypress Semiconductor Corporation does not authorize its products for use as critical components in life-support systems or critical medical instruments, where a malfunction or failure may reasonably be expected to result in significant injury to the user.
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01 Page 17 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Document Title: C9812 Low EMI Clock Generator for Intel(R) 810E Chipset Systems Document Number: 38-07053
Rev. **
ECN No. 107061
Issue Date 06/07/01
Orig. of Change IKA
Description of Change Convert from IMI to Cypress
Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01 Page 18 of 18

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